1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory device in which data can be electrically erased/written, such as a NOR type flash memory, and an electronic card and electronic apparatus in which the device is used, particularly to an erase control in a case where data of a large number of memory cells is collectively electrically erased.
2. Description of the Related Art
Among nonvolatile semiconductor memory device in which data can be electrically erased/written, in a block erasable flash memory, an electric charge of a floating gate of a memory cell transistor is changed by an erase/write operation to change a threshold voltage, and the data is stored. For example, when electrons of the floating gate are emitted to set the threshold voltage to a negative polarity, data “0” is stored. When the electrons are injected into the floating gate to set the threshold voltage to a positive polarity, data “1” is stored. The electrons are emitted/injected, for example, between the floating gate and a semiconductor substrate via a tunnel oxide film. Therefore, when the data is erased/written, the tunnel oxide film deteriorates, the electrons injected into the floating gate leak out of the tunnel oxide film, and it is difficult to retain the data. In the existing circumstances, a general-purpose flash memory allows 100 thousand to a million rewrites.
Additionally, in the NOR flash memory, a bias voltage having a negative polarity is applied to a gate of a memory cell, when block erasing. As the NOR flash memory, (1) a channel erasing in which the bias voltage having a positive polarity is applied to a source and a substrate or a well region and Fowler-Nordheim (FN) tunnel current is passed to erase the channel, (2) a negative gate erasing in which a bias voltage having a positive polarity is applied to the source and 0 V is applied to the substrate or well region, and the like have been known.
FIG. 1 shows one example of a sectional structure of a cell transistor in a memory cell array in the flash memory of the channel erasing.
In FIG. 1, reference numeral 11 denotes a P-type semiconductor substrate (PSUB), 11a denotes a P+-type substrate contact region, 12 denotes an N-type well region (NWELL), 13 denotes a P-type well region (PWELL), 12a denotes an N+-type well contact region, and 13a denotes a P+-type well contact region. In general, in the NOR type flash memory, a memory block to be collectively erased is 64 KBytes (=512 KBits). Therefore, the P-type well region 13 in which the memory cell is formed is divided for each memory block, and the respective P-type well regions 13 are electrically separated from each other. Moreover, a large number of memory cell transistors constituting each memory block are formed on each P-type well region 13.
FIG. 1 shows only one memory cell transistor. Reference numeral 14 denotes N+-type impurity diffusion layers formed as source and drain regions of the memory cell transistor, 15 denotes a gate insulating film which is formed on a channel region between the source and drain regions to function as a tunnel oxide film, 16 denotes a floating gate, 17 denotes a inter-gate insulating film composed, for example, of a stacked film (ONO film) of an oxide film/nitride film/oxide film, and 18 denotes a control gate. The control gate 18 is formed as a part of a word line. The drain region is connected to a bit line, and the source region is connected to a source line.
Table 1 shows one example of a voltage which has heretofore been supplied to each component of the transistor in operation modes of erase, write, read of the data in the memory cell transistor shown in FIG. 1.
TABLE 1OperationmodeVgVdVsVpwVnwRead+5 V+1 V0 V0 V0 VWrite+9 V+5 V0 V0 V0 VErase−7.5 V  FL+10 V   +10 V   +10 V   
When the data is erased, a drain potential Vd of the selected memory cell transistor is in a floating (FL) state, a control gate potential Vg is set to −7.5 V, and a source potential Vs and substrate potentials (well potentials) Vpw, Vnw are set to +10 V, respectively. At this time, the electrons injected beforehand in the floating gate 16 are pulled toward the P-type well region 13 via the tunnel oxide film 15 to erase the channel. Accordingly, the threshold voltage of the selected memory cell transistor is not more than a control gate voltage (e.g., +5 V) at the time of reading. This state is a memory state “0”.
The data is collectively erased with respect to all the memory cell transistors in a selected block. At this time, the word line and bit line of a non-selected block are in the floating state, and are set to high voltages by capacitive coupling with the P-type well region 13.
At the time of data writing, the source potential Vs and substrate potentials Vpw, Vnw of the selected memory cell transistor are set to 0 V, and the control gate potential Vg is set to +9 V. In this case, to write “1”, when the drain potential Vd is set to +5 V, the electrons are injected into the floating gate 16 from the channel region, and the threshold voltage of the memory cell transistor rises. Moreover, when the threshold voltage exceeds a certain value, the write is prohibited for each memory cell. On the other hand, when “0” is written, the drain potential Vd of the selected memory cell is set to 0 V, and the rise of the threshold voltage of the selected memory cell is prohibited.
At the time of data reading, the source potential Vs and substrate potentials Vpw, Vnw of the selected memory cell are set to 0 V, the drain potential Vd is set to +1 V, and the control gate potential Vg is set to a read voltage (+5 V). At this time, when the threshold voltage of the selected memory cell is not more than the read voltage (+5 V), the selected bit line and source line become conductive, and the potential of the bit line indicates a relatively low level “L”. On the other hand, when the threshold voltage of the selected memory cell is not less than the read gate voltage (+5 V), the selected bit line and source line become non-conductive, and the potential of the bit line indicates a relatively high level “H”.
In the channel erase flash memory, column redundancy and block redundancy are disposed as redundancy circuits for relieving various memory cell defects generated in the memory cell array. However, row redundancy is not employed for the following reasons.
That is, in a die sort test after forming a device on a wafer, when the word line in the memory cell array is found to have a short circuit with the P-type well region, a desired voltage is not applied to the word line and P-type well region. Therefore, the data is not erased in a defective block of a certain erase unit (e.g., a block constituted of 64 Kbytes) formed on the P-type well region. Therefore, the defective block has to be replaced with a redundancy block prepared beforehand in a memory chip. Since this redundancy block requires one independent memory operation, there is a penalty that a chip area increases with an increase of the number of blocks.
On the other hand, in the NOR type flash memory, there is a possibility of occurrence of a bit defect in which a drain contact of the memory cell transistor is in an open state, that is, erasable but not writable. In the NOR type flash memory, since two memory cells share one drain contact, pair bit defect easily occur. Additionally, there is also a possibility of occurrence of a single bit defect in which a defect exists simply in the channel region of one memory cell and a cell current indicates an abnormal value to cause the read defect.
There are various causes for the bit defect. When the defective bit is relieved using the block redundancy or the column redundancy, and when block relief is carried out, the defects can be completely eliminated. However, as described above, the block redundancy has a problem of penalty of the area, and is not desirable from a viewpoint of cost.
On the other hand, when the defective bit is relieved using the column redundancy, the erase voltage is applied to the defective bit at the time of erasing. Therefore, depending on the number of repeated write/erase operations, there is a risk that the defective bit shifts to an erase defect. In this manner, the column redundancy has the penalty of the area, but the penalty is not larger than that of the block redundancy, and this is advantageous from a cost aspect.
To relieve the above-described bit defect with the redundancy, to give a priority on the cost aspect, first the defect has heretofore been relieved with the column redundancy so as to minimize the block redundancy if possible. Overflow defect and the defect that can be relieved only with the block redundancy are relieved with the block redundancy.
However, when this relief is carried out, and when the write/erase operation is repeated in the memory cell, there occurs the short circuit between the word line and the well region. Even the bit defect in which the chip does not normally operate is replaced by the column redundancy. As a result, there is a risk that a market defect is caused.
It is to be noted that in Jpn. Pat. Appln. KOKAI Publication No. 7-320496 and T. Tanzawa, et al., “A 44-mm2 Four-Bank Eight-Word Page-Read 64-Mb Flash Memory With Flexible Block Redundancy and Fast Accurate Word-Line Voltage Controller”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002, in the above-described flash memory of a negative gate channel erasing, there is a redundancy. It is also disclosed that control means is disposed for preventing a negative potential bias for the erase only with respect to a defective row replaced with the spare row and the spare row not used in the replacement at the time of the erase.
As described above, in the conventional channel erase flash memory, when the bit defect is relieved with the redundancy, the write/erase operation is repeatedly performed in the memory cell, accordingly even the bit defect causing the short circuit between the word line and the well region is replaced with the column redundancy, and this has a risk of causing a market defect.
Therefore, there has heretofore been a demand for the channel erase flash memory in which the market defect involved in the bit defect causing the short circuit between the word line and the well region can be prevented from being generated.